ST8024CD datasheet(14/23 Pages) STMICROELECTRONICS

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ST8024

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Figure 6: Activation sequence at t3

ACTIVE MODE

When the activation sequence is completed, the ST8024 will be in its active mode. Data are exchanged

between the card and the microcontroller via the I/O lines.

The ST8024 is designed for cards without VPP (the voltage required to program or erase the internal

non-volatile memory).

DEACTIVATION SEQUENCE

When a session is completed, the microcontroller sets the CMDVCC line HIGH. The circuit then executes

an automatic deactivation sequence by counting the sequencer back and finishing in the inactive mode

(see Fig.7):

1. RST goes LOW (t10).

2. CLK is held LOW (t12 = t10 + 0.5 x T) where T is 64 times the period of the internal oscillator

(approximately 25 µs).

3. I/O, AUX1 and AUX2 are pulled LOW (t13 = t10 + T).

4. VCC starts to fall towards zero (t14 = t10 + 1.5 x T).

5. The deactivation sequence is complete at tde, when VCC reaches its inactive state.

6. VUP falls to zero (t15 = t10 + 5T) and all card contacts become low-impedance to GND; I/OUC, AUX1UC

and AUX2UC remain at VDD (pulled-up via a 11 kΩ resistor).

7. The internal oscillator returns to its lower frequency.

ST8024CD 数据表(PDF) 14 Page - STMicroelectronics