• Bus voltage underlimit (BUL)

• Power overlimit (POL)

The ALERT pin is an open-drain output. This pin is asserted when the alert function selected in the Mask/Enable

register exceeds the value programmed into the Alert Limit register. Only one of these alert functions can be

enabled and monitored at a time. If multiple alert functions are enabled, the selected function in the highest

significant bit position takes priority and responds to the Alert Limit register value. For example, if the SOL and

the SUL are both selected, the ALERT pin asserts when the Shunt Voltage Over Limit register exceeds the value

in the Alert Limit register.

The conversion-ready state of the device can also be monitored at the ALERT pin to inform the user when the

device has completed the previous conversion and is ready to begin a new conversion. The conversion ready

flag (CVRF) bit can be monitored at the ALERT pin along with one of the alert functions. If an alert function

and the CNVR bit are both enabled for monitoring at the ALERT pin, then after the ALERT pin is asserted, the

CVRF bit (D3) and the AFF bit (D4) in the Mask/Enable register must be read following the alert to determine the

source of the alert. If the conversion ready feature is not desired, and the CNVR bit is not set, the ALERT pin

only responds to an exceeded alert limit based on the alert function enabled.

If the alert function is not used, the ALERT pin can be left floating without impacting the operation of the device.

Refer to Figure 7-1 to see the relative timing of when the value in the Alert Limit register is compared to the

corresponding converted value. For example, if the alert function that is enabled is Shunt Voltage Over Limit

(SOL), following every shunt voltage conversion the value in the Alert Limit register is compared to the measured

shunt voltage to determine if the measurements have exceeded the programmed limit. The AFF bit (D4, Mask/

Enable register) asserts high any time the measured voltage exceeds the value programmed into the Alert Limit

register. In addition to the AFF bit being asserted, the ALERT pin is asserted based on the Alert Polarity bit

(APOL, D1, Mask/Enable register). If the Alert Latch is enabled, the AFF bit and ALERT pin remain asserted until

either the Configuration register is written to or the Mask/Enable register is read.

The bus voltage alert functions (BOL and BUL, Mask/Enable register) compare the measured bus voltage to

the Alert Limit register following every bus voltage conversion and assert the AFF bit and ALERT pin if the limit

threshold is exceeded.

The power overlimit alert function (POL, Mask/Enable register) is also compared to the calculated power value

following every bus voltage measurement conversion and asserts the AFF bit and ALERT pin if the limit

threshold is exceeded.

The alert function compares the programmed alert limit value to the result of each corresponding conversion.

Therefore, an alert can be issued during a conversion cycle where the averaged value of the signal does not

exceed the alert limit. Triggering an alert based on this intermediate conversion allows for out-of-range events

to be detected faster than the averaged output data registers are updated. This fast detection can be used to

create alert limits for quickly changing conditions through the use of the alert function, as well as to create limits

to longer-duration conditions through software monitoring of the averaged output values.

7.4 Device Functional Modes

7.4.1 Continuous verses Triggered Operation

The INA234 has two operating modes, continuous and triggered, that determine how the ADC operates

after these conversions. When the INA234 is in the normal operating mode (that is, the MODE bits of the

Configuration register are set to '111'), it continuously converts a shunt voltage reading followed by a bus voltage

reading.

In triggered mode, writing any of the triggered convert modes into the Configuration register (0h) (that is, the

MODE bits of the Configuration register are set to 001) triggers a single-shot conversion. This action produces a

single set of measurements. To trigger another single-shot conversion, the Configuration register must be written

to again, even if the mode does not change.

Although the INA234 can be read at any time, and the data from the last conversion remain available, the

conversion ready flag bit (CVRF bit, Mask/Enable register) is provided to help coordinate single-shot or triggered

INA234

SBOS844 – MAY 2021

www.ti.com

10

Submit Document Feedback

Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: INA234