Voltage peak-to-peak ripple due to ESR = V

PP-ESR

=

I

Voltage peak-to-peak ripple, root mean squared =

Note that the output ripple is dependent on the current ripple

and the equivalent series resistance of the output capacitor

(R

perature dependent); make sure that the frequency of the

R

frequency.

TABLE 2. Suggested Capacitors and Their Suppliers

Model

Description

Case

Size

Vendor

4.7µF for C

IN

C1608X5R0J475 Ceramic,

X5R, 6.3V

Rating

0603

TDK

C2012X5R0J475 Ceramic,

X5R, 6.3V

Rating

0805

JMK212BJ475

Ceramic,

X5R, 6.3V

Rating

0805

Taiyo

Yuden

GRM21BR60J475 Ceramic,

X5R, 6.3V

Rating

0805

muRata

GRM219R60J-

475KE19D

Ceramic,

X5R, 6.3V

Rating

0805(Thin)

Height

10µF C

OUT

C2012X5R0J106 Ceramic,

X5R, 6.3V

Rating

0805

TDK

JMK212BJ106

Ceramic,

X5R, 6.3V

Rating

0805

Taiyo

Yuden

GRM21BR60J106 Ceramic,

X5R, 6.3V

Rating

0805

muRata

GRM219R60J-

106KE19D

Ceramic,

X5R, 6.3V

Rating

0805(Thin)

Height

POR (POWER ON RESET)

The LM3370 has an independent POR functions (nPOR) for

each buck converter. The nPOR1 and nPOR2 are open

drain circuits which pull low when the outputs are below 94%

(rising V

inherent delay between the output (at 94% of V

time at which the nPOR is enabled is about 50ms. A pull up

resistor of 100k

Ω at nPOR pin is required. Please refer to the

electrical specification table for other timing options. The

diagram below illustrates the timing response of the POR

function.

20167319

SPREAD SPECTRUM (SS)

The LM3370 features Spread Spectrum capability, via I

reduce the noise amplitude of the switching frequency during

data transmission. The feature can be enabled by activating

the appropriate control register bit (see register information

section for detail). The main clock of the LM3370 features

spread spectrum, where : F

reduce noise caused by the harmonics present in the wave-

forms at the switch pins of the buck regulators. It is controlled

by I

I

Modulation Frequency

SS_fmod = 1 (default)

1 kHz

SS_fmod = 0

2 kHz

BOARD LAYOUT CONSIDERATIONS

PC board layout is an important part of DC-DC converter

design. Poor board layout can disrupt the performance of a

DC-DC converter and surrounding circuitry by contributing to

EMI, ground bounce, and resistive voltage loss in the traces.

These can send erroneous signals to the DC-DC converter

IC, resulting in poor regulation or instability.

Good layout for the LM3370 can be implemented by follow-

ing a few simple design rules:

1.

Place the LM3370, inductor and filter capacitors close

together and make the traces short. The traces between

these components carry relatively high switching cur-

rents and act as antennas. Following this rule reduces

radiated noise. Place the capacitors and inductor within

0.2 in. (5mm) of the LM3370.

2.

Arrange the components so that the switching current

loops curl in the same direction. During the first half of

each cycle, current flows from the input filter capacitor,

through the LM3370 and inductor to the output filter

capacitor and back through ground, forming a current

loop. In the second half of each cycle, current is pulled

up from ground, through the LM3370 by the inductor, to

the output filter capacitor and then back through ground,

forming a second current loop. Routing these loops so

the current curls in the same direction prevents mag-

netic field reversal between the two half-cycles and re-

duces radiated noise.

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