L6982CDR datasheet(47/48 Pages) STMICROELECTRONICS

47 / 48 page

List of figures

Figure 1.

Block diagram .................................................................... 2

Figure 2.

Pin connection (top view) ............................................................. 3

Figure 3.

Basic application (adjustable version) .................................................... 4

Figure 4.

Power up/down behavior ............................................................. 8

Figure 5.

Soft-start procedure ................................................................ 9

Figure 6.

Soft-start phase with ROUT = 3 Ω ...................................................... 10

Figure 7.

Light load operation................................................................ 11

Figure 8.

LCM operation with ISKIP = 40 mA typ. at zero load. L = 22 μH; COUT = 44 μF ....................... 11

Figure 9.

LCM operation over loading condition (part 1-pulse skipping) ................................... 12

Figure 10.

LCM operation over loading condition (part 2-pulse skipping) ................................... 12

Figure 11.

LCM operation over loading condition (part 3-pulse skipping) ................................... 13

Figure 12.

LCM operation over loading condition (part 4-CCM) ......................................... 13

Figure 13.

Low noise mode operation at zero load .................................................. 14

Figure 14.

Light-load efficiency for low consumption mode and low noise mode - linear scale..................... 15

Figure 15.

Light-load efficiency for low consumption mode and low noise mode - log scale ...................... 15

Figure 16.

Load regulation for LCM and LNM. VIN = 24 V; VOUT = 5 V; FSW = 400 KHz - linear scale ............... 16

Figure 17.

Load regulation for low noise mode. VIN = 24 V; VOUT = 5 V; FSW = 400 KHz - log scale ................ 16

Figure 18.

OVP event low noise mode part number ................................................. 17

Figure 19.

OVP event low consumption mode part number ............................................ 18

Figure 20.

Over current protection behavior ....................................................... 19

Figure 21.

Soft-start procedure with VOUT shorted to GND ............................................ 20

Figure 22.

Over current procedure with persistent short circuit between VOUT and GND ........................ 20

Figure 23.

Block diagram of the loop............................................................ 21

Figure 24.

Trans-conductance embedded error amplifier .............................................. 22

Figure 25.

Leading network example ........................................................... 23

Figure 26.

Leading network example ........................................................... 24

Figure 27.

External synchronization. Direct connection ............................................... 24

Figure 28.

External synchronization. AC coupling ................................................... 25

Figure 29.

Application circuit ................................................................. 26

Figure 30.

Evaluation board schematic .......................................................... 29

Figure 31.

Top layer ....................................................................... 30

Figure 32.

Bottom layer..................................................................... 30

Figure 33.

Efficiency VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHZ .......................................... 31

Figure 34.

Efficiency VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHZ (log scale)................................... 31

Figure 35.

Power losses VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHZ ........................................ 32

Figure 36.

Efficiency VIN = 12 V; VOUT = 5 V; FSW = 0.4 MHZ .......................................... 32

Figure 37.

Efficiency VIN = 12 V; VOUT = 5 V; FSW = 0.4 MHZ (log scale)................................... 33

Figure 38.

Power losses VIN = 12 V; VOUT = 5 V; FSW = 0.4 MHZ ........................................ 33

Figure 39.

Efficiency VIN = 24 V; VOUT = 3.3 V; FSW = 0.4 MHZ......................................... 34

Figure 40.

Efficiency VIN = 24 V; VOUT = 3.3 V; FSW = 0.4 MHZ (log scale) ................................. 34

Figure 41.

Power losses VIN = 24 V; VOUT = 3.3 V; FSW = 0.4 MHZ ...................................... 34

Figure 42.

Efficiency VIN = 12 V; VOUT = 3.3 V; FSW = 0.4 MHZ ......................................... 35

Figure 43.

Efficiency VIN = 12 V; VOUT = 3.3 V; FSW = 0.4 MHZ (log scale) ................................. 35

Figure 44.

Power losses VIN = 12 V; VOUT = 3.3 V; FSW = 0.4 MHZ ...................................... 36

Figure 45.

Switching losses .................................................................. 38

Figure 46.

SO 8L package outline ............................................................. 40

Figure 47.

SO 8L recommended footprint ........................................................ 41

L6982

List of figures

DS13683 - Rev 1

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