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EVAL-AD1839EB 数据表(PDF) 13 Page - Analog Devices

部件名 EVAL-AD1839EB
功能描述  2 ADC, 6 DAC, 96 kHz, 24-Bit sigma-delta Codec
PDF  24 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

EVAL-AD1839EB 数据表(HTML) 13 Page - Analog Devices

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REV. B
AD1839
–13–
CLATCH
CCLK
CIN
COUT
D0
D8
D0
D15
D14
D9
D8
tCCH tCCL
D9
tCDS tCDH
tCLS
tCLH
tCOD
tCOTS
tCCP
tCOE
Figure 3. Format of SPI Timing
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LEFT CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
I2S MODE—16 BITS TO 24 BITS PER CHANNEL
RIGHT-JUSTIFIED MODE—S ELECT NUMBER OF BITS PER CHANNEL
DSP MODE—16 BITS TO 24 BITS PER CHANNEL
1/
fS
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT
fS EXCEPT FOR DSP MODE WHICH IS 2
fS.
3. BCLK FREQUENCY IS NORMALLY 64
LRCLK BUT MAY BE OPERATED IN BURST MODE.
Figure 4. Stereo Serial Modes



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