ADRF6821 datasheet(8/61 Pages) AD

部件名	ADRF6821

功能描述	450 MHz to 2800 MHz, DPD RFIC with Integrated Fractional-N PLL and VCO

PDF	61 Pages

Scroll/Zoom	100%

制造商	AD [Analog Devices]

网页	http://www.analog.com

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8 / 61 page

ADRF6821

Data Sheet

Rev. A | Page 8 of 61

SERIAL PERIPHERAL INTERFACE (SPI) TIMING SPECIFICATIONS

Table 6.

Parameter

Symbol

Min

Typ

Max

Unit

TIMING REQUIREMENTS

SDI to SCLK Rising Edge Setup

tDS

SCLK Rising Edge to SDI Hold

tDH

Period of SCLK

tCLK

CS Falling Edge to SCLK Rising Edge, Setup Time

SCLK Rising Edge to CS Rising Edge, Hold Time

SCLK Falling Edge to Valid Readback Data, SDIO or SDO (Not Shown in Figure 2)

tDV

SCLK

Period of SCLK for a Logic High State

tHIGH

Period of SCLK for a Logic Low State

tLOW

SPI Timing Diagram

DON’T CARE

SCLK

SDIO

R/W

A14

A13

A12

A11

A10

DON’T CARE

tDS

tHIGH

tDH

tLOW

tCLK

Figure 2. SPI Write (MSB First), 16-Bit Instruction, Timing Measurements

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