TQFP N.

QFN N.

Name

Type

Function

40

45

OUT2

Power

Phase 2 high-side (floating) common

voltage

41

46

HVG2(1)

Analog Out

Phase 2 high-side driver output

42

47

BOOT2

Power

Phase 2 bootstrap supply voltage

46

51

OUT3

Power

Phase 3 high-side (floating) common

voltage

47

52

HVG3(1)

Analog Out

Phase 3 high-side driver output

48

53

BOOT3

Power

Phase 3 bootstrap supply voltage

50

58

RES5

Reserved

Pin must be left floating

51

59

VCC

Power

Driver low side and logic supply voltage

52

60

RES1

Reserved

Pin must be left floating

53

61

RES2

Reserved

Pin must be left floating

54

62

RES3

Reserved

Pin must be left floating

55

63

PA12

I/O - FT

MCU PA12

56

64

PA13

I/O - FT

MCU PA13/SWDIO (System debug data)

57

65

PA14

I/O - FT

MCU PA14/SWDCLK (System debug clock)

58

66

PA15

I/O - FT

MCU PA15

59

67

PB3

I/O - FT

MCU PB3

60

68

PB4

I/O - FT

MCU PB4

61

69

PB5

I/O - FT

MCU PB5

62

70

PB6

I/O - FTf

MCU PB6

63

71

PB7

I/O - FTf

MCU PB7

64

72

BOOT0

I - B

Boot memory selection

32, 36, 37,

38, 39, 43,

44, 45, 49

44

NC

Not Connected

-

-

EPAD

Power

Exposed pad, internally connected to

SGND

“bleeder” resistor connected between the gate and the source of the external MOSFETs normally used to hold the pin low.

When the EN is set low, gate driver outputs are forced low and assure low impedance.

STSPIN32F0251, STSPIN32F0252

Pin description table

DS13048 - Rev 4

page 7/32