MCP39F511N datasheet(21/61 Pages) MICROCHIP

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DS20005473B-page 21

MCP39F511N

5.0

CALCULATION ENGINE (CE)

DESCRIPTION

5.1

Computation Cycle Overview

The MCP39F511N uses a coherent sampling algorithm

to phase lock the sampling rate to the line frequency on

the voltage channel input with an integer number of

samples per line cycle, and reports all power output

quantities at a 2N number of line cycles. This is defined

as a computation cycle and is dependent on the line

frequency, so any change in the line frequency will

change the update rate of the power outputs.

There are two separate computation paths, using two

currents from two separate channels (channel 1 and

channel 2) referenced below as IN and V. Therefore

each current, power, and energy output is duplicated,

one for each calculation channel.

In addition, there are duplicate calibration registers

(offset, gain, phase, etc.) for each calculation channel.

5.1.1

LINE FREQUENCY

The coherent sampling algorithm is also used to

calculate the Line Frequency Output register, which is

updated every computation cycle. The correction factor

for line frequency measurement is the Gain Line

Frequency register, which is used during the line

frequency calibration (see section Section 9.6.1

“Using

the

Auto-Calibrate

Frequency

Command”. Note that the resolution of the Line

Frequency Output register is fixed, and the resolution is

1mHz.

5.2

Accumulation Interval Parameter

The accumulation interval is defined as a 2N number of

line cycles, where N is the value in the Accumulation

Interval Parameter register. This is identical for both

calculation channels.

5.3

Raw Voltage and Currents Signal

Conditioning

The first set of signal conditioning that occurs inside the

MCP39F511N is shown in Figure 5-1. All conditions set

in this diagram affect all of the output registers (RMS

current, RMS voltage, Active power, Reactive power,

apparent power, etc.). The gain of the PGA, the

Shutdown and Reset status of the 24-bit ADCs are all

controlled through the System Configuration Register.

To compensate for any external phase error between

the current and voltage channels, the Phase

Compensation register can be used.

See Section 9.0 “MCP39F511N Calibration” for

more information on device calibration.

FIGURE 5-1:

Channels 1 or 2 (IN and V) Input-Signal Flow.

CHANNEL IN

24-bit

 ADC

Multi-Level

Modulator



CHANNEL V

10-bit SAR ADC

HPF (1)



PhaseCompensation1:s16

HPF (1)

PGA

IN+

IN-

V+

SystemConfiguration:b32

Note

High-Pass Filters (HPFs) are automatically disabled in the absence of an AC signal on the voltage channel.

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