MCP48CVB01 datasheet(53/106 Pages) MICROCHIP

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 2019 Microchip Technology Inc.

DS20006160A-page 53

MCP48CXBXX

Technology Status Register. The width of this register is

2 times the number of DACs for the device.

WiperLock Technology bits only control access to

volatile memory. Nonvolatile memory write access is

controlled by the requirement of high voltage on the

HVC pin, which is recommended to not be available

during normal device operation.

WIPERLOCK TECHNOLOGY CONTROL REGISTER (1BH)

(NONVOLATILE)

U-0

R/W-n R/W-n R/W-n R/W-n

Single

——

———

—

——

—(1)

WL0B WL0A

Dual

——

———

—

——

WL1B WL1A WL0B WL0A

bit 15

bit 0

Legend:

R = Readable bit

W = Writable bit

C = Clearable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

= Single-channel device

= Dual-channel device

Single

Dual

bit 15-2

bit 15-4

Unimplemented: Read as ‘0’

bit 1-0

bit 3-0

WLXB-WLXA: WiperLock™ Technology Status bits(2)

11 = Vol. DAC Wiper Register and Vol. DAC configuration bits are locked

10 = Vol. DAC Wiper Register is locked, and Vol. DAC configuration bits are unlocked

01 = Vol. DAC Wiper Register is unlocked, and Vol. DAC configuration bits are locked

00 = Vol. DAC Wiper Register and Vol. DAC configuration bits are unlocked

Note 1:

Unimplemented bit, read as ‘0’.

The volatile PDxB:PDxA bits are NOT locked due to the requirement of being able to exit Power-Down

mode.

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