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MCP48CMB02 数据表(PDF) 67 Page - Microchip Technology |
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MCP48CMB02 数据表(HTML) 67 Page - Microchip Technology |
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67 / 106 page  2019 Microchip Technology Inc. DS20006160A-page 67 MCP48CXBXX 6.6.1 OPERATION IN SPI MODE 0,0 In SPI Mode 0,0: • SCK idle state = Low (VIL) • Data is clocked in on the SDI pin on the rising edge of SCK • Data is clocked out on the SDO pin on the falling edge of SCK 6.6.2 OPERATION IN SPI MODE 1,1 In SPI Mode 1,1: • SCK idle state = High (VIH) • Data is clocked in on the SDI pin on the rising edge of SCK • Data is clocked out on the SDO pin on the falling edge of SCK FIGURE 6-2: 24-Bit Commands (Write, Read) - SPI Waveform (Mode 0,0). FIGURE 6-3: 24-Bit Commands (Write, Read) - SPI Waveform (Mode 1,1). CS SCK Write to SSPBUF SDI Input Sample SDO bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 bit15 bit14 bit1 bit0 bit23 bit22 bit21 bit20 bit16 bit15 bit14 bit1 bit0 AD4 AD3 AD2 AD1 C1 D16 D15 D14 D1 D0 VIH VIL CMDERR bit 7.5V HVC VIH VIH C0 bit19 AD0 Note: HVC must be at VIHH before start of a Write command and only lowered to VIH or VIL after MTP write cycle ••• ••• ••• ••• ••• ••• ••• ••• completes (MTPMA bit). Also shadow PD0B:PD0A = ‘00” (so that Band Gap circuitry is operational) CS SCK Write to SSPBUF SDI Input Sample SDO bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 bit15 bit14 ••• bit1 bit0 bit23 bit22 bit21 bit20 C0 bit16 bit15 bit14 bit1 bit0 AD4 AD3 AD2 AD1 bit19 C1 D16 D15 D14 D1 D0 VIH VIL CMDERR bit 7.5V HVC VIH AD0 Note: HVC must be at VIHH before start of a Write command and only lowered to VIH or VIL after MTP write cycle ••• ••• ••• ••• ••• ••• ••• completes (MTPMA bit). Also shadow PD0B:PD0A = ‘00” (so that Band Gap circuitry is operational) VIH |
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