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MCP48CMB22 数据表(PDF) 3 Page - Microchip Technology |
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MCP48CMB22 数据表(HTML) 3 Page - Microchip Technology |
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3 / 106 page  2019 Microchip Technology Inc. DS20006160A-page 3 MCP48CXBXX MCP48CVBX2 Block Diagram (Dual-Channel Output) VDD VSS Memory VREF0(3) VREF1:VREF0 Note 1: Available only on specific packages. 2: On dual output devices, except those in a QFN16 package, the LAT0 pin is internally connected to LAT1 input of DAC1. 3: On dual output devices, except those in a QFN16 package, the VREF0 pin is internally connected to VREF1 input of DAC1. VOUT0 VDD LAT0/HVC PD1:PD0 VREF1:VREF0 OPAMP PD1:PD0 and VREF1:VREF0 DAC0 and DAC1 VREF POWER-DOWN GAIN STATUS DAC0 and DAC1 VREF POWER-DOWN GAIN WIPERLOCK™ VOLATILE (5 x 16) NONVOLATILE (14 x 16) Power-up/Brown-out Control SPI Serial Interface Module and Control Logic (WiperLock™ Technology) Band gap 1.214V VDD GAIN VREF1(3) VREF1:VREF0 VOUT1 VDD LAT1(2) PD1:PD0 VREF1:VREF0 OPAMP PD1:PD0 and VREF1:VREF0 VDD GAIN VIHH LAT0 LAT0(2) VBG VBG SCK SDI SDO CS |
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