MCP47FVB21 datasheet(59/92 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS20005429B-page 59

MCP48FEBXX

7.1.3

CONTINUOUS WRITES TO

VOLATILE MEMORY

A Continuous Write mode of operation is possible when

writing to the device’s volatile memory registers (see

Table 7-3). Figure 7-4 shows the sequence for three

continuous writes. The writes do not need to be to the

same volatile memory address.

7.1.4

CONTINUOUS WRITES TO

NONVOLATILE MEMORY

Continuous writes to nonvolatile memory are not

allowed, and attempts to do so will result in a

Command Error (CMDERR) condition.

7.1.5

THE HIGH VOLTAGE COMMAND

(HVC) SIGNAL

If the state of the HVC pin is VIHH, then the command

is ignored, but a Command Error condition (CMDERR)

will NOT be generated.

FIGURE 7-3:

Write Command - SDI and SDO States.

TABLE 7-3:

VOLATILE MEMORY

ADDRESSES

Address

Single-Channel

Dual-Channel

00h

Yes

01h

Yes

08h

Yes

09h

Yes

0Ah

Yes

00 C

111111111111111111111111 Valid (1)

1111111

0Invalid (2, 3)

Address

Data bits (8, 10, or 12 bits)

SDI

SDO

Command

Note 1:

If a valid Address/Command occurs, then the data bits are dependent on the resolution of the device.

12-bit = D11:D00, 10-bit = D09:D00, and 8-bit = D07:D00. Data is right justified for ease of Host Controller

operation (i.e., no data manipulation before transmitting the desired value).

Unimplemented data bits (D15:D12 on 12-bit device, D15:D10 on 10-bit device, D15:D08 on 8-bit device)

will be output as ‘1’.

If an Error condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR condition

is cleared (the CS pin is forced to the inactive state).

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