1/13

April 2004

s

s

LOW POWER DISSIPATION:

s

HIGH NOISE IMMUNITY:

s

SYMMETRICAL OUTPUT IMPEDANCE:

s

BALANCED PROPAGATION DELAYS:

s

WIDE OPERATING VOLTAGE RANGE:

s

PIN AND FUNCTION COMPATIBLE WITH

54 SERIES 193

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SPACE GRADE-1: ESA SCC QUALIFIED

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50 krad QUALIFIED, 100 krad AVAILABLE ON

REQUEST

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NO SEL UNDER HIGH LET HEAVY IONS

IRRADIATION

s

DEVICE FULLY COMPLIANT WITH

SCC-9204-065

DESCRIPTION

The

M54HC193

is

an

high

speed

CMOS

SYNCRONOUS

UP/DOWN

BINARY

technology.

The counter has two separate clock inputs, an UP

COUNT input and a DOWN COUNT input. All

outputs

of

the

flip-flop

are

simultaneously

triggered on the low to high transition of either

clock while the other input is held high. The

direction of counting is determined by which input

is clocked. This counter may be preset by entering

the desired data on the DATA A, DATA B, DATA

C, and DATA D input. When the LOAD input is

taken low the data is loaded independently of

either clock input. This feature allows the counters

to be used as divide-by-n counters by modifying

the count length with the preset inputs. In addition

the

counter

can

also

be

cleared.

This

is

accomplished by inputting a high on the clear

input. All 4 internal stages are set to low

independently of either COUNT input. Both a

BORROW and CARRY output are provided to

enable cascading of both up and down counting

functions. The BORROW output produces a

negative going pulse when the counter underflows

and the CARRY outputs a pulse when the

counters overflows. The counter can be cascaded

by connection the CARRY and BORROW outputs

of one device to the COUNT UP and COUNT

DOWN inputs, respectively, of the next device.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

M54HC193

RAD-HARD SYNCHRONOUS UP/DOWN BINARY COUNTER

PIN CONNECTION

ORDER CODES

PACKAGE

FM

EM

DILC

M54HC193D

M54HC193D1

FPC

M54HC193K

M54HC193K1

DILC-16

FPC-16