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HD26LS32AP 数据表(PDF) 1 Page - Renesas Technology Corp |
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HD26LS32AP 数据表(HTML) 1 Page - Renesas Technology Corp |
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1 / 8 page ![]() Rev.2.00, Jul.16.2004, page 1 of 7 HD26LS32A Quadruple Differential Line Receivers With 3 State Outputs REJ03D0296–0200Z (Previous ADE-205-578 (Z)) Rev.2.00 Jul.16.2004 Description The HD26LS32A features quadruple line receivers designed to meet the specs of EIA standard RS-422A and RS-423. This device operates from a single 5 V power supply. The enable function is common to all four receivers and offers a choice of active high or active low input. Fail safe design ensures that if the inputs are open, the outputs will always be high. Features • Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD26LS32AP DILP-16 pin (JEITA) DP-16E, -16FV P — Logic Diagram 1A Enable G Enable G 1Y 2Y 3Y 4Y 1B 2A 2B 3A 3B 4A 4B |
类似零件编号 - HD26LS32AP |
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类似说明 - HD26LS32AP |
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