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MCP48FVB24 数据表(PDF) 21 Page - Microchip Technology |
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MCP48FVB24 数据表(HTML) 21 Page - Microchip Technology |
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21 / 112 page  2020 Microchip Technology Inc. DS20006362A-page 21 MCP48FXBX4/8 TABLE 1-5: SPI REQUIREMENTS (MODE 0,0) # Characteristic Sym. Min. Max. Units Conditions SCK Input Frequency FSCK —10 MHz VDD = 2.7V to 5.5V (READ command) —20 MHz VDD = 2.7V to 5.5V (all other commands) 70 CS Active (VIL) to SCK Input TCSA2SCH 60 — ns 71 SCK Input High Time TSCH 20 — ns VDD = 2.7V to 5.5V 400 — ns VDD = 1.8V to 2.7V 72 SCK Input Low Time TSCL 20 — ns VDD = 2.7V to 5.5V 400 — ns VDD = 1.8V to 2.7V 73 Setup Time of SDI Input to SCK Edge TDIV2SCH 10 — ns 74 Hold Time of SDI Input from SCK Edge TSCH2DIL 20 — ns 77 CS Inactive (VIH) to SDO Output High-Impedance TCSH2DOZ —50 ns Note 1 80 SDO Data Output Valid after SCK Edge TSCL2DOV —45 ns VDD = 2.7V to 5.5V —170 ns VDD = 1.8V to 2.7V 82 SDO Data Output Valid after CS Active (VIL)TSSL2DOV —70 ns 83 CS Inactive (VIH) after SCK Edge TSCH2CSL 100 — ns VDD = 2.7V to 5.5V 1µs VDD = 1.8V to 2.7V 84 CS High Time (VIH)TCSH 50 — ns 94 LAT to SCK ↑ (write data 24th bit) Setup Time TLATSU 10 — ns Write data transferred(3) 96 LAT High or Low Time TLAT 50 — ns 97 HVC to SCK (1st data bit) (HVC setup time) THVCSU 0 — ns High-Voltage Commands(1) 98 SCK (last bit of command, 8th or 24th bit) to HVC (HVC hold time) THVCHD 25 — ns High-Voltage Commands(1) Note 1: This parameter is ensured by design. 3: Within 1/2 LSb of the final value when the code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12-bit device.) The transition of the LAT signal must occur 10 ns before the rising edge of the 24th SCK signal (Spec 94) or the current register data value may not be transferred to the output latch (VOUT) before the register is overwritten with the new value. |
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