ACE25AC200GL

2M SPI NOR FLASH

VER 1.2

11

Sector Erase (SE) (20H)

The Sector Erase (SE) command is for erasing the all data of the chosen sector. A Write Enable (WREN)

command must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase

(SE) command is entered by driving CS# low, followed by the command code, and 3-address byte on SI.

Any address inside the sector is a valid address for the Sector Erase (SE) command. CS# must be driven

low for the entire duration of the sequence.

The Sector Erase command sequence: CS# goes low→sending Sector Erase command→3-byte address

on SI→CS# goes high. The command sequence is shown in Figure8. CS# must be driven high after the

eighth bit of the last address byte has been latched in; otherwise the Sector Erase (SE) command is not

initiated.

While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the

Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle,

and is 0 when it is completed. Write Enable Latch (WEL) bit is reset to 0 at the end of the Sector Erase

cycle. Sector Erase (SE) command applied to a sector which is protected by the Block Protect (BP2, BP1,

BP0) bit (see Table1) is not executed.

Block Erase (BE) (D8H)

The Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN)

command must previously have been executed to set the Write Enable Latch (WEL) bit. The Block Erase

(BE) command is entered by driving CS# low, followed by the command code, and three address bytes

on SI. Any address inside the block is a valid address for the Block Erase (BE) command. CS# must be

driven low for the entire duration of the sequence.

The Block Erase command sequence: CS# goes low send Block Erase command 3-byte address on

SI

C S # goe s high. The c om m a

e driven high after the

eighth bit of the last address byte has been latched in; otherwise the Block Erase (BE) command is not

executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is

initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of

the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase

cycle, and is 0 when it is completed. Write Enable Latch (WEL) bit is reset to 0 at the end of the Block

Erase cycle. Block Erase (BE) commands applied to a block which is protected by the Block Protect (BP2,

BP1, BP0) bits (see Table1) is not executed.

Figure8. Sector Erase Sequence Diagram

Figure9. Block Erase Sequence Diagram