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PIMXRT516SCVM2A 数据表(PDF) 51 Page - NXP Semiconductors |
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PIMXRT516SCVM2A 数据表(HTML) 51 Page - NXP Semiconductors |
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51 / 124 page ![]() Electrical characteristics i.MX RT1160 Crossover Processors Data Sheet for Extended Industrial Products, Rev. 0, 04/2021 NXP Semiconductors 51 4.4.1 Reset timing parameters Figure 9 shows the POR reset timing and Table 40 lists the timing parameters. Figure 9. POR reset timing diagram 4.4.2 WDOG reset timing parameters Figure 10 shows the WDOG reset timing and Table 41 lists the timing parameters. Figure 10. WDOGn_B timing diagram NOTE RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or approximately 30 s. NOTE WDOGn_B output signals (for each one of the Watchdog modules) do not have dedicated pins, but are muxed out through the IOMUX. See the IOMUX manual for detailed information. Table 40. POR reset timing parameters ID Parameter Min Max Unit CC1 Duration of POR_B to be qualified as valid. 1 — RTC_XTALI cycle Table 41. WDOGn_B timing parameters ID Parameter Min Max Unit CC3 Duration of WDOGn_B Assertion 1 — RTC_XTALI cycle POR_B CC1 (Input) WDOGn_B CC3 (Output) |
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