MP8799

9

Rev. 3.00

Analog Input Multiplexer

The MP8799 includes a 8-Channel analog input multiplexer.

The relationship between the clock, the multiplexer address, the

WR and the output data is shown in

Figure 10.

Figure 10. MUX Address Timing

WR

Clock

DB0-DB9

Address

Sample N

Old Address

Sample M

New Address

Sample

M+1

N-2 Valid

N-1 Valid

Old Address

N Valid

Old Address

M Valid

New Address

A2, A1, A0

MUXEN

(Internal Signal)

WR

Figure 11. Analog MUX Timing

Reference Voltages

DATA = 1023

Digital Interfaces

The logic encodes the outputs of the comparators into a bi-

nary code and latches the data in a D-type flip-flop for output.

The functional equivalent of the MP8799 (

Figure 12.) is com-

posed of:

1)

(

φ

2)

3)

delay.

4)

table.

Figure 12. MP8799 Functional Equivalent

Circuit and Interface Timing

φ

S

A/D

MP8799

CLK

DB9-DB0

N

N+1

N-1

N

DQ

DQ

DB9-DB0

CLK