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ACE34AC04FMTH 数据表(PDF) 7 Page - ACE Technology Co., LTD.

部件名 ACE34AC04FMTH
功能描述  4K I2C Serial EEPROM with Software Write Protection
PDF  22 Pages
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制造商  ACE [ACE Technology Co., LTD.]
网页  http://www.ace-ele.com
标志 ACE - ACE Technology Co., LTD.

ACE34AC04FMTH 数据表(HTML) 7 Page - ACE Technology Co., LTD.

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ACE34AC04
4K I
2C Serial EEPROM with Software Write Protection
VER 1.1
7
Device Addressing
The ACE34AC04 requires a 7-bit device address and a Read/Write select bit following a Start condition
from the Master to initiate communication with the Serial EEPROM. The device address byte is comprised
of a 4-bit device type identifier followed by three device address bits (A2, A1, and A0) and a R/W bit and is
clocked by the Master on the SDA pin with the most significant bit first .The ACE34AC04 will respond to
two unique device type identifiers. The device type identifier of ‘1010’(Ah) is necessary to select the
device for reading or writing. The device type identifier of ‘0110’(6h) has multiple purposes. First, it is used
to access the page address function which determines what the internal address counter is set to. The
device type identifier of ‘0110’(6h) is also used to access the software write protection feature of the
device.
Table 1: Device Address Byte
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read/Write
Device Type Identifier
Device Address
EEPROM
Read/Write
1
0
1
0
A2
A1
A0
R/ W
Write Protection and
Page Address
Functions
0
1
1
0
A2
A1
A0
R/ W
The software device address bits (A2, A1, and A0) must match their corresponding hard-wired device
address inputs (A2, A1 and A0) allowing up to eight devices on the bus at the same time. The eighth bit of
the address byte is the R/W operation selection bit. A read operation is selected if this bit is a Logic 1, and
a Write operation is selected if this bit is a Logic 0. Upon a compare of the device address byte, the
ACE34AC04 will output an ACK during the ninth clock cycle; if a compare is not true, the device will
output a NACK during the ninth clock cycle and return the device to the low-power Standby Mode.
Table 2: Device Address Combinations
Software Device Address Bits
Hard-wired Device Address Inputs
A2, A1, A0
A2
A1
A0
000
GND
GND
GND
001
GND
GND
V
CC
010
GND
V
CC
GND
011
GND
V
CC
V
CC
100
V
CC
GND
GND
101
V
CC
GND
V
CC
110
V
CC
V
CC
GND
111
V
CC
V
CC
V
CC



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