ACE25QC800GLDPTH datasheet(26/58 Pages) ACE

26 / 58 page

ACE25QC800G

8M BIT SPI NOR FLASH

VER 1.2

Quad I/O Fast Read (EBH)

See Figure 13, the Quad I/O Fast Read instruction is similar to the Dual I/O Fast Read instruction but with

the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock

4-bit per clock by IO0, IO1, IO3, IO4, each bit being latched in during the rising edge of SCLK, then the

memory contents are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The first byte addressed can

be at any location. The address is automatically incremented to the next higher address after each byte of

data is shifted out. The Quad Enable bit (QE) of Status Register must be set to enable for the Quad I/O Fast

read instruction.

Quad I/O Fast Read with “Continuous Read Mode”

The Quad I/O Fast Read instruction can further reduce instruction overhead through setting the

“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 13, If the

“Continuous Read Mode” bits (M5-4 )= (1,0), then the next Fast Read Quad I/O instruction(after /CS is

raised and then lowered) does not require the EBH instruction code, The instruction sequence is shown in

the followed Figure 14. If the “Continuous Read Mode” bits M5-4 do not eQuad to (1,0), the next instruction

requires the first EBH instruction code, thus returning to normal operation. A “Continuous Read Mode”

Reset command can also be used to reset (M5-4) before issuing normal command.

Figure12. Dual I/O Fast Read Sequence Diagram (Previous command set (M5-4) =(1,0))

ACE25QC800GLDPTH 数据表(PDF) 26 Page - ACE Technology Co., LTD.