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ICS950403 数据表(PDF) 7 Page - Integrated Circuit Systems

部件名 ICS950403
功能描述  AMD - K8??System Clock Chip
PDF  18 Pages
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制造商  ICST [Integrated Circuit Systems]
网页  http://www.icst.com
标志 ICST - Integrated Circuit Systems

ICS950403 数据表(HTML) 7 Page - Integrated Circuit Systems

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7
ICS950403
Advance Information
0732—01/27/03
I
2C Table: Read back
Control
Function
Bit 7
WDHRB
WD Hard Alarm Status
Read back
R-
-
X
Bit 6
WDSRB
WD Soft Alarm Status
Read back
R-
-
X
Bit 5
24_48SEL
24_48SEL pin Control
R
By S/W
By Latched
1
Bit 4
FS3
FS3 on POR state
R
By S/W
By Latched
1
Bit 3
FS2
FS2 on POR state
R
By S/W
By Latched
1
Bit 2
FS1
FS1 on POR state
R
By S/W
By Latched
1
Bit 1
FS0
FS0 on POR state
R
By S/W
By Latched
1
Bit 0
Reserved
Reserved
R
-
-
0
I
2C Table: Output Control Register
Control
Function
Bit 7
HTTCLK0
Output Control
RW
Disable
Enable
1
Bit 6
PCICLK9/HTTCLK3
Output Control
RW
Disable
Enable
1
Bit 5
PCICLK8/HTTCLK2
Output Control
RW
Disable
Enable
1
Bit 4
PCICLK7/HTTCLK1
Output Control
RW
Disable
Enable
1
Bit 3
PCICLK_F
Output Control
RW
Disable
Enable
1
Bit 2
Reserved
Reserved
RW
-
-
0
Bit 1
Reserved
Reserved
RW
-
-
0
Bit 0
Reserved
Reserved
RW
-
-
0
I
2C Table: Byte Count Register
Control
Function
Bit 7
BC7
RW
-
-
0
Bit 6
BC6
RW
-
-
0
Bit 5
BC5
RW
-
-
0
Bit 4
BC4
RW
-
-
0
Bit 3
BC3
RW
-
-
1
Bit 2
BC2
RW
-
-
1
Bit 1
BC1
RW
-
-
1
Bit 0
BC0
RW
-
-
1
I
2C Table: Vendor and Revision ID Register
Control
Function
Bit 7
RID3
R
-
-
0
Bit 6
RID2
R
-
-
0
Bit 5
RID1
R
-
-
0
Bit 4
RID0
R
-
-
0
Bit 3
VID3
R
-
-
0
Bit 2
VID2
R
-
-
0
Bit 1
VID1
R
-
-
0
Bit 0
VID0
R
-
-
1
-
-
-
-
-
-
-
Byte 7
Pin #
-
-
PWD
-
Type
Name
0
1
Writing to this register
will configure how
many bytes will be read
back, default is 0F = 15
bytes.
-
-
Byte 6
Pin #
23
-
-
-
6
11
8
7
-
Byte 5
Pin #
Name
-
-
-
-
-
Name
Type
Byte 4
Pin #
-
-
PWD
Name
0
Type
PWD
PWD
1
Type
0
1
-
-
-
-
REVISION ID
VENDOR ID
01



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