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MPC885ZP66 数据表(PDF) 49 Page - NXP Semiconductors |
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MPC885ZP66 数据表(HTML) 49 Page - NXP Semiconductors |
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49 / 87 page  MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor 49 CPM Electrical Characteristics 12.3 IDMA Controller AC Electrical Specifications Table 18 provides the IDMA controller timings as shown in Figure 48 tthrough Figure 51. Figure 48. IDMA External Requests Timing Diagram Table 18. IDMA Controller Timing Num Characteristic All Frequencies Unit Min Max 40 DREQ setup time to clock high 7 — ns 41 DREQ hold time from clock high 1 1 Applies to high-to-low mode (EDM = 1). TBD — ns 42 SDACK assertion delay from clock high — 12 ns 43 SDACK negation delay from clock low — 12 ns 44 SDACK negation delay from TA low — 20 ns 45 SDACK negation delay from clock high — 15 ns 46 TA assertion to rising edge of the clock setup time (applies to external TA)7 — ns 41 40 DREQ (Input) CLKO (Output) |
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