KMPC885ZP133 datasheet(72/87 Pages) NXP

72 / 87 page

MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7

Freescale Semiconductor

FEC Electrical Characteristics

Figure 73 shows MII receive signal timing.

Figure 73. MII Receive Signal Timing Diagram

15.2

MII and Reduced MII Transmit Signal Timing

The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz + 1%. The

RMII transmitter functions correctly up to a RMII_REFCLK maximum frequency of 50 MHz + 1%.

There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the

MII_TX_CLK frequency – 1%.

Table 35 provides information on the MII and RMII transmit signal timing.

Table 35. MII Transmit Signal Timing

Num

Characteristic

Min

Max

Unit

MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid

—

MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid

—

M20_RMII

RMII_TXD[1:0], RMII_TX_EN to RMII_REFCLK setup

—

M21_RMII

RMII_TXD[1:0], RMII_TX_EN data hold from RMII_REFCLK rising

edge

2—

MII_TX_CLK and RMII_REFCLK pulse width high

35%

65%

MII_TX_CLK or

RMII_REFCLK

period

MII_TX_CLK and RMII_REFCLK pulse width low

35%

65%

MII_TX_CLK or

RMII_REFCLK

period

MII_RX_CLK (Input)

MII_RXD[3:0] (Inputs)

MII_RX_DV

MII_RX_ER

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