M25P128 datasheet(9/41 Pages) STMICROELECTRONICS

部件名	M25P128

功能描述	128 Mbit (Multilevel), Low Voltage, Serial Flash Memory With 50MHz SPI Bus Interface

PDF	41 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

标志

9 / 41 page

M25P128

SPI modes

Rev. 1

9/41

SPI modes

These devices can be driven by a microcontroller with its SPI peripheral running in either of

the two following modes:

●

CPOL=0, CPHA=0

●

CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising edge of Serial Clock (C), and

output data is available from the falling edge of Serial Clock (C).

The difference between the two modes, as shown in Figure 5, is the clock polarity when the

bus master is in Stand-by mode and not transferring data:

●

C remains at 0 for (CPOL=0, CPHA=0)

●

C remains at 1 for (CPOL=1, CPHA=1)

Figure 4.

Bus Master and Memory Devices on the SPI Bus

The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.

Figure 5.

SPI Modes Supported

AI03746e

Bus Master

(ST6, ST7, ST9,

ST10, Others)

SPI Memory

Device

SDO

SDI

SCK

CQD

SPI Memory

Device

CQD

SPI Memory

Device

CQD

CS3

CS2

CS1

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

HOLD

R(2)

VCC

AI01438B

MSB

CPHA

CPOL

MSB

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