VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC880

High Performance 16x16

Serial Crosspoint Switch

G52191-0, Rev 4.2

Page 21

01/05/01

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Table 3: Receive Data Output Timing Table

Figure 11: CPU Interface Write Cycle Timing

Figure 12: CPU Interface Read Cycle Timing

Table 4: CPU Interface Timing Table

Parameter

Description

Min

Typ

Max

Units

Interrupt pulse width

15

ns

RESET, RESYNEN pulse width

64

ns

Parameter

Description

Min

Typ

Max

Units

CSEL falling edge to valid address

5

ns

CSEL inactive between read cycles

10

ns

CWEN valid to CSEL falling edge

5

ns

CSEL active to CWEN change

5

ns

Valid data and address during a write

45

ns

CSEL low time during a write

20

ns

CSEL cycle time during a write

55

ns

CSEL active to valid data

15

45

ns

CSEL deactivate to high impedance data

5

ns

CSEL active to low impedance data

0

ns

ADDR[5:0]

CWEN

CDATA[7:0]

CSEL

Valid Data

Valid Address

ADDR[5:0]

CWEN

CDATA[7:0]

CSEL

Valid Data

Valid Address

Hi-Z

Hi-Z