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MPC9850 数据表(PDF) 8 Page - Freescale Semiconductor, Inc |
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MPC9850 数据表(HTML) 8 Page - Freescale Semiconductor, Inc |
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8 / 12 page  Advanced Clock Drivers Devices 8 Freescale Semiconductor MPC9850 Table 12. MPC9850 Pin Diagram (Top View) 1 2 345 678 9 10 A VDDOA VDDOA CLKA[1] CLKA[3] CLKA[5] VDD QA1 QA2 VDDOA VDDOA B VDDOA VDDOA CLKA[0] CLKA[2] CLKA[4] QA0 VDDOA QA3 VDDOA VDDOA C RSVD RSVD VDD VDD VDD VDD VDD VDD VDD REF_OUT D VDDA VDDA VDD GNDGND GNDGND VDD QC0 QC0 E REF_SEL CLK VDD GNDGND GNDGND VDD VDDOC GND F PCLK PCLK VDD GNDGND GNDGND VDD QC1 QC1 G REF_CLK_SEL REF_33MHz VDD GNDGND GNDGND VDD PLL_BYPASS MR H XTAL_IN XTAL_OUT VDD VDD VDD VDD VDD VDD RIO_C[1] RIO_C[0] J VDDOB VDDOB CLKB[0] CLKB[2] CLKB[4] QB0 VDDOB QB3 VDDOB VDDOB K VDDOB VDDOB CLKB[1] CLKB[3] CLKB[5] VDD QB1 QB2 VDDOB VDDOB Table 13. MPC9850 Pin List Signal 100 Pin MAPBGA Signal 100 Pin MAPBGA Signal 100 Pin MAPBGA Signal 100 Pin MAPBGA Signal 100 Pin MAPBGA VDDOA A1 RSVD(1) 1. RSVD pins must be left open. C1 REF_SEL E1 REF_CLK_SEL G1 VDDOB J1 VDDOA A2 RSVD(1) C2 CLK E2 REF_33MHz G2 VDDOB J2 CLKA[1] A3 VDD C3 VDD E3 VDD G3 CLKB[0] J3 CLKA[3] A4 VDD C4 GND E4 GND G4 CLKB[2] J4 CLKA[5] A5 VDD C5 GND E5 GND G5 CLKB[4] J5 VDD A6 VDD C6 GND E6 GND G6 QB0 J6 QA1 A7 VDD C7 GND E7 GND G7 VDDOB J7 QA2 A8 VDD C8 VDD E8 VDD G8 QB3 J8 VDDOA A9 VDD C9 VDDOC E9 PLL_BYPASS G9 VDDOB J9 VDDOA A10 REF_OUT C10 GND E10 MR G10 VDDOB J10 VDDOA B1 VDDA D1 PCLK F1 XTAL_IN H1 VDDOB K1 VDDOA B2 VDDA D2 PCLK F2 XTAL_OUT H2 VDDOB K2 CLKA[0] B3 VDD D3 VDD F3 VDD H3 CLKB[1] K3 CLKA[2] B4 GND D4 GND F4 VDD H4 CLKB[3] K4 CLKA[4] B5 GND D5 GND F5 VDD H5 CLKB[5] K5 QA0 B6 GND D6 GND F6 VDD H6 VDD K6 VDDOA B7 GND D7 GND F7 VDD H7 QB1 K7 QA3 B8 VDD D8 VDD F8 VDD H8 QB2 K8 VDDOA B9 QC0 D9 QC1 F9 RIO_C[1] H9 VDDOB K9 VDDOA B10 QC0 D10 QC1 F10 RIO_C[0] H10 VDDOB K10 |
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