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Evaluates: MAX17536

5V Output-Voltage Application

MAX17536EVKITB# Evaluation Kit

Detailed Description

The MAX17536 EV kit provides a proven design to evaluate

the high-voltage, high-efficiency, synchronous step-down

DC-DC converter. The EV kit is preset for a 5V output from

a 6.5V to 60V input at load currents up to 4A and features

a 450kHz switching frequency for optimum efficiency and

component size.

The EV kit includes an EN/UVLO PCB pad and JU1 to

enable the output at a desired input voltage. The SYNC

PCB pad allows an external clock to synchronize the

device. JU2 allows the selection of a particular mode of

operation based on light-load performance requirements.

An additional RESET PCB pad is available for monitoring

when the converter output is in regulation.

Soft-Start Input (SS)

The device utilizes an adjustable soft-start function to

limit inrush current during startup. The soft-start time is

adjusted by the value of the external capacitor from SS to

of C7, as shown by the following equation:

equation:

For example, to program a 2.2ms soft-start time, C7

should be 12nF.

Regulator Enable/Undervoltage-Lockout Level

(EN/UVLO)

The device offers an adjustable-input, undervoltage-

lockout level. For normal operation, a shunt should be

installed across pins 1-2 on JU1. To disable the output,

install a shunt across pins 2-3 on JU1 and the EN/UVLO

pin is pulled to GND. See Table 1 for JU1 settings.

Set the voltage at which the device turns on with the

resistive voltage-divider R1/R2 connected from VIN_ to

SGND. Connect the center node of the divider to EN/

UVLO. Choose R1 to be 3.32MΩ and then calculate R2

as follows:

R2 = R1 x 1.215

VINU - 1.215

where VINU is the voltage at which the device is required

to turn on.

Mode/SYNC Selection (MODE)

The device’s MODE pin can be used to select among the

PWM, PFM, or DCM modes of operation. The logic state

voltages exceed the respective UVLO rising thresholds

and all internal voltages are ready to allow LX switching.

State changes on the MODE pin are ignored during normal

operation. Refer to the MAX17536IC data sheet for more

information on the PWM, PFM, and DCM modes of operation.

Table 2 lists JU2 jumper settings that can be used to

configure the desired mode of operation. The internal

oscillator of the device can be synchronized to an external

clock signal on the SYNC pin. The external synchronization

minimum external clock high pulse width should be greater

than 50ns, while the minimum external clock low pulse width

should be greater than 160ns.

Table 1. Regulator Enable (EN/UVLO)

Description (JU1)

Table 2. MODE Description (JU2)

*Default position.

*Default position.

SHUNT

POSITION

EN/UVLO PIN

MAX17536_

OUTPUT

1-2*

Connected to VIN

Enabled

Not installed

Connected to the center

node of resistor-divider

R1 and R2

Enabled, UVLO

level set through

the R1 and R2

resistors

2-3

Connected to SGND

Disabled

SHUNT POSITION

MODE PIN

MAX17536_ MODE

Not installed*

Unconnected

PFM mode of

operation

1-2

Connected to

SGND

PWM mode of

operation

2-3

Connected to

VCC

DCM mode of

operation