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STW8019 数据表(PDF) 47 Page - STMicroelectronics |
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STW8019 数据表(HTML) 47 Page - STMicroelectronics |
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47 / 55 page ![]() STw8009/STw8019 Electrical characteristics 47/55 7.3 Electrical and timing characteristics Unless otherwise specified: TA=+25°C, all voltages are referenced to GND. ) Table 23. 2 wire serial MPU control interface timing ( Figure 15) Symbol Parameter Test Conditions Min. Typ. Max. Unit fSCL Clock Frequency 400 Khz tBUF Bus free time 1300 ns tHD_STA Start condition hold time 600 ns tf SDA & SCLK fall time 300 ns tLOW SCLK pulse width low 1300 ns tr SDA & SCLK rise time 300 ns tHIGH SCLK pulse width high 600 ns tHD_DAT Data input hold time 0 ns tSU_DAT Data input set up time 250 ns tSU_STA Start condition set up time 600 ns tSU_STO Stop condition set up time 600 ns Table 24. Digital I/O interface Symbol Parameter Test Conditions Min. Typ. Max. Unit VIL Input Low voltage All digital inputs 0.4 V VIH Input High voltage All digital inputs 1.3 V VOL Output Low level All digital outputs 0.2 V VOH Output High level All digital outputs 1.6 V IIL Input Low current All digital inputs / 0V < Vin < VIL -10 10 µA IIH Input High current All digital inputs / VCCIO < Vin < VIH -10 10 µA Table 25. YcbCr data bus timing Symbol Parameter Test Conditions Min. Typ. Max. Unit FCLK Clock Frequency 27 MHz TCLKHIGH Clock pulse width high 15 ns TCLKLOW Clock pulse width low 15 ns DATHD Data input hold time TBD ns DATSU Data input set up time TBD ns |
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