1/10

May 2004

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HIGH SPEED:

s

LOW POWER DISSIPATION:

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HIGH NOISE IMMUNITY:

s

SYMMETRICAL OUTPUT IMPEDANCE:

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BALANCED PROPAGATION DELAYS:

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WIDE OPERATING VOLTAGE RANGE:

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PIN AND FUNCTION COMPATIBLE WITH

54 SERIES 4514

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SPACE GRADE-1: ESA SCC QUALIFIED

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50 krad QUALIFIED, 100 krad AVAILABLE ON

REQUEST

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NO SEL UNDER HIGH LET HEAVY IONS

IRRADIATION

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DEVICE FULLY COMPLIANT WITH

SCC-9205-019

DESCRIPTION

The M54HC4514 is an high speed CMOS 4 LINE

TO

16

LINE

SEGMENT

DECODER

WITH

LATCHED INPUTS fabricated with silicon gate

A binary code stored in the four input latches (A to

D) provides a high level at the selected one of

sixteen outputs excluding the other fifteen outputs,

when the inhibit input (INHIBIT) is held low. When

the inhibit input (INHIBIT) is held high, all outputs

are kept low level, while the latch function is

available. The data applied to the data inputs are

transferred to the Q outputs of latches when the

strobe input is held high. When the strobe input is

taken low, the information data applied to the data

input at a time is retained at the output of the

latches.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

M54HC4514

RAD-HARD 4 TO 16 LINE DECODER/LATCH

PIN CONNECTION

ORDER CODES

PACKAGE

FM

EM

DILC

M54HC4514D

M54HC4514D1

FPC

M54HC4514K

M54HC4514K1

DILC-24

FPC-24

Rev. 1