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M69AW024BE 数据表(PDF) 13 Page - STMicroelectronics |
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M69AW024BE 数据表(HTML) 13 Page - STMicroelectronics |
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13 / 25 page ![]() 13/25 M69AW024BE Table 7. Read and Standby Modes AC Characteristics Note: 1. The maximum value of this timing is applicable if E1 is kept Low with addresses unchanged.If needed by the system operation, please contact your local ST representative for relaxation of the 1000ns limitation. 2. Addresses should not be changed during tAVAX(min). 3. These parameters are measured according to the conditions on input and output timing reference voltage shown on Figure 6., AC Measurement I/O Waveform. 4. The output load capacitance is 5pF without any other load. 5. These timings are given for E1 Low. 6. tAVAX(min) must be satisfied. 7. If the current value of tWHGL is lower than the minimum value given in the above table, tAVQV during the following Read operation may increase by tWHGL(current) – tWHGL(min). 8. All timings are measured according to the conditions for output transition timing reference voltage shown on Figure 6., AC Mea- surement I/O Waveform. Symbol Alt. Parameter M69AW024BE Unit –60 Min Max tAVAX, tELEH (1,2) tRC Read Cycle Time 70 1000 ns tELQV (3) tCE Chip Enable Access Time 60 ns tGLQV (3) tOE Output Enable Access Time 40 ns tAVQV (3,5) tAA Address Access Time 60 ns tBLQV (3) tBA LB, UB Low to Output Valid 30 ns tAXQX, tGHQX, tBHQX, tEHQX (8) tOH Output Hold Time after Chip Enable Low 5 ns tELQX (4,8) tCLZ Chip Enable Low to Output Low-Z 5 ns tGLQX (4,8) tOLZ Output Enable Low to Output Low-Z 0 ns tBLQX (4,8) tBLZ LB, UB Low to Output Low-Z 0 ns tEHQZ (8) tCHZ Chip Enable High to Output Hi-Z 20 ns tGHQZ (8) tOHZ Output Enable High to Output Hi-Z 20 ns tBHQZ (8) tBHZ LB, UB High to Output Hi-Z 20 ns tAVEL tASC Address Set-up Time to Chip Enable Low –5 ns tAVGL tASO Address Valid to Output Enable Low 10 ns tAXAV (5) tAX Address Invalid Time 10 ns tEHAX (6) tCHAH Chip Enable High to Address Hold Time –5 ns tGHAX tOHAH Output Enable High to Address Hold Time –5 ns tWHGL (7) tWHOL Write Enable High to Output Enable Low (Read Operations) 10 1000 ns tEHEL tCP Chip Enable High Pulse Width 10 ns |
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