TLF5326

January 1988

MM54HC237MM74HC237

3-to-8 Line Decoder With Address Latches

General Description

These devices utilize advanced silicon-gate CMOS technol-

ogy to implement a three-to-eight line decoder with latches

on the three address inputs When GL goes from low to

high the address present at the select inputs (A B and C) is

stored in the latches As long as GL remains high no ad-

dress changes will be recognized Output enable controls

G1 and G2 control the state of the outputs independently of

the select or latch-enable inputs All of the outputs are low

unless G1 is high and G2 is low The ’HC237 is ideally suit-

ed for the implementation of glitch-free decoders in stored-

address applications in bus oriented systems

The 54HC74HC logic family is speed function and pin-out

compatible with the standard 54LS74LS logic family All

inputs are protected from damage due to static discharge by

Features

Y

Typical propagation delay 20 ns

Y

Wide supply range 2 – 6V

Y

Latched inputs for easy interfacing

Y

Fanout of 10 LS-TTL loads

Connection Diagram

Dual-In-Line Package

TLF5326 – 1

Top View

Order Number MM54HC237 or MM74HC237

Truth Table

INPUTS

OUTPUTS

ENABLE

SELECT

GL

G1

G2

C

B

A

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

XX

H

X

X

X

L

L

LLLLLL

X

L

X

X

X

X

L

L

LLLLLL

LH

L

L

L

L

H

L

LLLLLL

LH

L

L

L

H

L

H

LLLLLL

LH

L

L

H

L

L

L

H

L

LLLL

LH

L

L

H

H

L

L

L

H

LLLL

LH

L

H

L

L

L

L

LL

H

LLL

LH

L

H

L

H

L

L

LLL

H

LL

LH

L

H

H

L

L

L

LLLL

H

L

LH

L

H

H

H

L

L

LLLLL

H

HH

L

X

X

X

Output corresponding to stored

address L all others H

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A