DSPIC33EP64GS802T-ESLASHML datasheet(39/484 Pages) MICROCHIP

39 / 484 page

 2016-2018 Microchip Technology Inc.

DS70005258C-page 39

dsPIC33EPXXXGS70X/80X FAMILY

4.3

Data Address Space

The dsPIC33EPXXXGS70X/80X family CPU has a

separate 16-bit wide data memory space. The Data

Space is accessed using separate Address Generation

Units (AGUs) for read and write operations. The data

memory map is shown in Figure 4-6.

All Effective Addresses (EAs) in the data memory space

are 16 bits wide and point to bytes within the Data

Space. This arrangement gives a base Data Space

address range of 64 Kbytes or 32K words.

The lower half of the data memory space (i.e., when

EA<15> = 0) is used for implemented memory

addresses, while the upper half (EA<15> = 1) is

reserved for the Program Space Visibility (PSV).

dsPIC33EPXXXGS70X/80X family devices implement

up to 12 Kbytes of data memory. If an EA points to a

location outside of this area, an all-zero word or byte is

returned.

4.3.1

DATA SPACE WIDTH

The data memory space is organized in byte-

addressable, 16-bit wide blocks. Data is aligned in data

memory and registers as 16-bit words, but all Data

Space EAs resolve to bytes. The Least Significant

Bytes (LSBs) of each word have even addresses, while

the Most Significant Bytes (MSBs) have odd

addresses.

4.3.2

DATA MEMORY ORGANIZATION

AND ALIGNMENT

To maintain backward compatibility with PIC® MCU

devices and improve Data Space memory usage

efficiency, the dsPIC33EPXXXGS70X/80X family

instruction set supports both word and byte operations.

As a consequence of byte accessibility, all Effective

Address calculations are internally scaled to step

through word-aligned memory. For example, the core

recognizes that Post-Modified Register Indirect

Addressing mode [Ws++] results in a value of Ws + 1

for byte operations and Ws + 2 for word operations.

A data byte read, reads the complete word that

contains the byte, using the LSb of any EA to determine

which byte to select. The selected byte is placed onto

the LSB of the data path. That is, data memory and

registers are organized as two parallel, byte-wide

entities with shared (word) address decode, but

separate write lines. Data byte writes only write to the

corresponding side of the array or register that matches

the byte address.

All word accesses must be aligned to an even address.

Misaligned word data fetches are not supported, so

care must be taken when mixing byte and word

operations, or translating from 8-bit MCU code. If a

misaligned read or write is attempted, an address error

trap is generated. If the error occurred on a read, the

instruction underway is completed. If the error occurred

on a write, the instruction is executed but the write does

not occur. In either case, a trap is then executed,

allowing the system and/or user application to examine

the machine state prior to execution of the address

Fault.

All byte loads into any W register are loaded into the

LSB; the MSB is not modified.

A Sign-Extend (SE) instruction is provided to allow user

applications to translate 8-bit signed data to 16-bit

signed values. Alternatively, for 16-bit unsigned data,

user applications can clear the MSB of any W register

by executing a Zero-Extend (ZE) instruction on the

appropriate address.

4.3.3

SFR SPACE

The first 4 Kbytes of the Near Data Space, from

0x0000 to 0x0FFF, is primarily occupied by Special

Function Registers (SFRs). These are used by the

dsPIC33EPXXXGS70X/80X family core and peripheral

modules for controlling the operation of the device.

SFRs are distributed among the modules that they

control and are generally grouped together by module.

Much of the SFR space contains unused addresses;

these are read as ‘0’.

4.3.4

NEAR DATA SPACE

The 8-Kbyte area, between 0x0000 and 0x1FFF, is

referred to as the Near Data Space. Locations in this

space are directly addressable through a 13-bit absolute

address field within all memory direct instructions. Addi-

tionally, the whole Data Space is addressable using MOV

instructions, which support Memory Direct Addressing

mode with a 16-bit address field, or by using Indirect

Addressing mode using a Working register as an

Address Pointer.

Note:

The actual set of peripheral features and

interrupts varies by the device. Refer to

the corresponding device tables and

pinout

diagrams

for

device-specific

information.

DSPIC33EP64GS802T-E/ML 数据表(PDF) 39 Page - Microchip Technology

DSPIC33EP64GS802T-E/ML 数据表(HTML) 39 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载