数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

DSPIC33EP64GS802T-E/MM 数据表(PDF) 84 Page - Microchip Technology

部件名 DSPIC33EP64GS802T-E/MM
功能描述  16-Bit Digital Signal Controllers for Digital Power Applications with Interconnected High-Speed PWM, ADC, PGA and Comparators
PDF  484 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

DSPIC33EP64GS802T-E/MM 数据表(HTML) 84 Page - Microchip Technology

Back Button DSPIC33EP64GS802T-E/MM Datasheet HTML 80Page - Microchip Technology DSPIC33EP64GS802T-E/MM Datasheet HTML 81Page - Microchip Technology DSPIC33EP64GS802T-E/MM Datasheet HTML 82Page - Microchip Technology DSPIC33EP64GS802T-E/MM Datasheet HTML 83Page - Microchip Technology DSPIC33EP64GS802T-E/MM Datasheet HTML 84Page - Microchip Technology DSPIC33EP64GS802T-E/MM Datasheet HTML 85Page - Microchip Technology DSPIC33EP64GS802T-E/MM Datasheet HTML 86Page - Microchip Technology DSPIC33EP64GS802T-E/MM Datasheet HTML 87Page - Microchip Technology DSPIC33EP64GS802T-E/MM Datasheet HTML 88Page - Microchip Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 84 / 484 page
background image
dsPIC33EPXXXGS70X/80X FAMILY
DS70005258C-page 84
 2016-2018 Microchip Technology Inc.
REGISTER 7-1:
SR: CPU STATUS REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/C-0
R/C-0
R-0
R/W-0
OA
OB
SA
SB
OAB
SAB
DA
DC
bit 15
bit 8
R/W-0(3)
R/W-0(3)
R/W-0(3)
R-0
R/W-0
R/W-0
R/W-0
R/W-0
IPL2(2)
IPL1(2)
IPL0(2)
RA
N
OV
Z
C
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’= Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3)
111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
Note 1:
For complete register details, see Register 3-1.
2:
The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL, if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3:
The IPL<2:0> Status bits are read-only when the NSTDIS bit (INTCON1<15>) = 1.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com