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DM74LS353M 数据表(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 DM74LS353M
功能描述  Dual 4-Input Multiplexer with TRI-STATE-R Outputs
PDF  6 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

DM74LS353M 数据表(HTML) 3 Page - National Semiconductor (TI)

  DM74LS353M Datasheet HTML 1Page - National Semiconductor (TI) DM74LS353M Datasheet HTML 2Page - National Semiconductor (TI) DM74LS353M Datasheet HTML 3Page - National Semiconductor (TI) DM74LS353M Datasheet HTML 4Page - National Semiconductor (TI) DM74LS353M Datasheet HTML 5Page - National Semiconductor (TI) DM74LS353M Datasheet HTML 6Page - National Semiconductor (TI)  
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Switching Characteristics
VCC ea50V TA ea25 C
Symbol
Parameter
RL e 2kX CL e 50 pF
Units
Min
Max
tPLH
Propagation Delay
24
ns
tPHL
Sn to Zn32
tPLH
Propagation Delay
15
ns
tPHL
In to Zn15
tPZH
Output Enable Time
18
ns
tPZL
OE to Zn
18
tPHZ
Output Disable Time
18
ns
tPLZ
OE to Zn
18
Functional Description
The ’LS353 contains two identical 4-input multiplexers with
TRI-STATE outputs They select two bits from four sources
selected by common Select inputs (S0 S1) The 4-input
multiplexers have individual Output Enable (OEa) OEb) in-
puts which when HIGH force the outputs to a high imped-
ance (high Z) state The logic equations for the outputs are
shown below
If the outputs of TRI-STATE devices are tied together all
but one device must be in the high impedance state to avoid
high currents that would exceed the maximum ratings De-
signers should ensure that Output Enable signals to TRI-
STATE devices whose outputs are tied together are de-
signed so that there is no overlap
Za e OEa  (I0a  S1  S0 a I1a  S1  S0 a I2a  S1  S0 a I3a  S1  S0)
Zb e OEb  (I0b  S1  S0 a I1b  S1  S0 a I2b  S1  S0 a I3b  S1  S0)
Truth Table
Select
Data Inputs
Output
Output
Inputs
Enable
S0
S1
I0
I1
I2
I3
OE
Z
X
X
XXXX
H
(Z)
L
L
L
XXX
L
H
L
L
H
XXX
L
L
H
L
XLX
X
L
H
H
L
XHX
X
L
L
L
H
X
XLX
L
H
L
H
X
XHX
L
L
H
H
XXX
L
L
H
H
H
XXX
H
L
L
Address inputs S0 and S1 are common to both sections
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
(Z) e High Impedance
3



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