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STM6718 数据表(PDF) 4 Page - STMicroelectronics |
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STM6718 数据表(HTML) 4 Page - STMicroelectronics |
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4 / 25 page ![]() STM6717/6718/6719/6720/6777/6778/6779*/6780* 4/25 SUMMARY DESCRIPTION The STM6717/18/19/20 and STM6777/78/79/80 Supervisors are a family of low voltage/low supply current processor (Micro or DSP) Supervisors, de- signed to monitor two (or three) system power supply voltages. They are targeted at applications such as Set-Top Boxes (STBs), portable, battery- powered systems, networking, and communica- tion systems. All device options have a push-button-type manu- al reset input (MR). The STM6777/78/79/80 also includes an option which enables the user to delay the start of the Manual Reset process from 6µs (MRC pin left open) or more with external capaci- tor. The delay is implemented by connecting the appropriately sized capacitor between the MRC pin and VSS (typical 4s delay with a 3.3µF capaci- tor, see Table 7., page 19). Two of the three supplies monitored (VCC1 and VCC2) have fixed (customer-selectable, factory- trimmed) thresholds (VRST1 and VRST2). The third voltage is monitored using an externally adjust- able RSTIN threshold (0.626V internal reference). If any of the three monitored voltages drop below its factory-trimmed or adjustable thresholds, or if MR is asserted to logic low, a RST is asserted (driven low). Once asserted, RST is maintained at Low for a minimum delay period (trec) after ALL supplies rise above their respective thresholds and MR returns to High. These devices are guar- anteed to be in the correct reset output logic state when VCC1 and/or VCC2 is greater than 0.8V. These devices are available in a standard 5-pin or 6-pin SOT23 packages (see Table 1., page 1). Figure 2. Logic Diagram (STM6717/18) Figure 3. Logic Diagram (STM6719/20) Figure 4. Logic Diagram (STM6777/78) Figure 5. Logic Diagram (STM6779/80) AI10413 VCC1 STM6717 STM6718 VSS VCC2 RST MR AI10414 VCC1 STM6719 STM6720 VSS VCC2 RST RSTIN MR AI10415 VCC1 STM6777 STM6778 VSS VCC2 RST MRC MR AI10416 VCC STM6779 STM6780 VSS RST MRC RSTIN MR |
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