2

3495B–DFLSH–8/05

AT26DF041

To allow for simple in-system reprogrammability, the AT26DF041 does not require high input

voltages for programming. The device operates from a single power supply, 3.0V to 3.6V or

2.7V to 3.6V, for both the program and read operations. The AT26DF041 is enabled through

the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input

(SI), Serial Output (SO), and the Serial Clock (SCK).

All program and erase cycles are self-timed, and no separate erase cycle is required when

using the Page Program with Auto-Erase feature.

2.

Block Diagram

3.

Memory Array

To provide optimal flexibility, the memory array of the AT26DF041 is divided into three levels

of granularity comprising of sectors, blocks, and pages. The Memory Architecture Diagram

illustrates the breakdown of each level and details the number of pages per sector and block.

All program operations to the DataFlash occur either on a byte basis or on a page-by-page

basis; however, the optional erase operations can be performed at the block or page level.

FLASH MEMORY ARRAY

PAGE (256 BYTES)

BUFFER (256 BYTES)

WP

LOGIC

I/O INTERFACE

SCK

CS

VCC

GND

WP

SO

SI

STATUS

REGISTER