PLL620-05/-06/-07/-08/-09
Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal)
Universal Low Phase Noise IC’s
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 4
4. Jitter Specifications
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Period jitter RMS
2.5
Period jitter peak-to-peak
At 155.52MHz, with capacitive decoupling
between VDD and GND. Over 10,000
cycles
18.5
20
ps
Accumulated jitter RMS
2.5
Accumulated jitter peak-to-peak
At 155.52MHz, with capacitive decoupling
between VDD and GND. Over 1,000,000
cycles.
24
27
ps
Random Jitter
“RJ” measured on Wavecrest SIA 3000
2.5
ps
Integrated jitter RMS at 155MHz
Integrated 12 kHz to 20 MHz
0.3
0.4
ps
Period jitter RMS
11
Period jitter peak-to-peak
At 622.08MHz, with capacitive decoupling
between VDD and GND. Over 10,000
cycles
45
49
ps
Accumulated jitter RMS
11
Accumulated jitter peak-to-peak
At 622.08MHz, with capacitive decoupling
between VDD and GND. Over 1,000,000
cycles.
24
27
ps
Random Jitter
“RJ” measured on Wavecrest SIA 3000
3
ps
Integrated jitter RMS at 622MHz
Integrated 12 kHz to 20 MHz
1.6
1.8
ps
5. Phase Noise Specifications
PARAMETERS
FREQUENCY
@10Hz
@100Hz
@1kHz
@10kHz
@100kHz
UNITS
155.52MHz
-75
-95
-125
-140
-145
Phase Noise relative
to carrier
622.08MHz
-75
-95
-110
-125
-120
dBc/Hz
6. CMOS Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
IOH
VOH= VDD-0.4V, VDD=3.3V
30
mA
Output drive current
(High Drive)
IOL
VOL = 0.4V, VDD = 3.3V
30
mA
IOH
VOH= VDD-0.4V, VDD=3.3V
10
mA
Output drive current
(Standard Drive)
IOL
VOL = 0.4V, VDD = 3.3V
10
mA
Output Clock Rise/Fall Time
(Standard Drive)
0.3V ~ 3.0V with 15 pF load
2.4
Output Clock Rise/Fall Time
(High Drive)
0.3V ~ 3.0V with 15 pF load
1.2
ns
* Note: High Drive CMOS is available on PLL620-06 through DRIVSEL selector input on pin 12.
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