Analog Frequency Multiplier

VCXO Family of Products

47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991

www.phaselink.com

Rev.:03-22-05 Page 2

O s c illa to r

A m p lifie r

O E CT RL

Q

Q BAR

F requen c y

X2

XIN

XO U T

L2X

VC o n

F requen c y

X4

L4X

O n ly required in x 4 des igns

Figure 2: Overall VCXO AFM Block Diagram

Figure 3 shows the jitter histogram of the 2x Analog Frequency Multiplier at 155.52MHz, while figure 4 shows the very low

rejection levels of sub-harmonics that correspond to the exceptionally low jitter performance.

Figure 3: Jitter Histogram at 311.04 MHz

Figure 4: Spectrum Analysis at 311.04 MHz

Analog Frequency Multiplier (2x)

Analog Frequency Multiplier (2x)

with 155.52MHz crystal

with sub-harmonic below –72 dBc

OE LOGIC SELECTION

OUTPUT

OESEL

OE

Output State

0 (Default)

Enabled

0 (Default)

1

Tri-state

0

Tri-state

PECL

1

1 (Default)

Enabled

0

Tri-state

0 (Default)

1 (Default)

Enabled

0 (Default)

Enabled

LVDS or CMOS

1

1

Tri-state

OESEL and OE: Connect to VDD to set to “1”, connect to GND to set to “0”. Internally set to default through pull-down / -up.