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PL580-68OCL-R 数据表(PDF) 5 Page - PhaseLink Corporation |
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PL580-68OCL-R 数据表(HTML) 5 Page - PhaseLink Corporation |
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5 / 10 page ![]() (Preliminary) PL580-68/69 320-640MHz Low Phase Noise VCXO 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 5 4. General Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Supply Current, Dynamic (with Loaded Outputs) IDD PECL/LVDS 320MHz<Fout<640MHz 90/70 mA Operating Voltage VDD 2.97 3.63 V Output Clock Duty Cycle @ 50% VDD (CMOS) @ 1.25V (LVDS) @ VDD – 1.3V (PECL) 45 45 45 50 50 50 55 55 55 % Short Circuit Current ±50 mA 5. Jitter Specifications PARAMETERS CONDITIONS FREQUENCY MIN. TYP. MAX. UNITS 320.0MHz 0.4 0.5 Integrated jitter RMS Integrated 12 kHz to 20 MHz 622.08MHz 0.4 0.6 ps 320.0MHz 3 5 Period jitter RMS With capacitive decoupling between VDD and GND. Over 10,000 cycles. 622.08MHz 6 8 ps 320.0MHz 25 30 Period jitter Peak-to- Peak With capacitive decoupling between VDD and GND. Over 10,000 cycles. 622.08MHz 40 50 ps 6. Phase Noise Specifications PARAMETERS FREQ. @10Hz @100Hz @1kHz @10kHz @100kHz @1M @10M UNITS 320.0MHz -59 -86 -116 -129 -124 -140 -148 Phase Noise2 relative to carrier (typical) 622.08MHz -48 -80 -108 -118 -114 -131 -138 dBc/Hz |
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