Preliminary

PL611-30

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991

www.phaselink.com Rev 03/03/05 Page 2

KEY PROGRAMMING PARAMETERS

CLK[ 0:2 ]

Output Frequency

Output Drive

Strength

Crystal

Load

Programmable

Input/Output (pin #7)

# of

Register

Banks

Charge-Pump

Current

Fout = FIN * M / (R * P)

where M= 6 bit

R= 1

P= 5 bit

1. CLK[0:1]= VCO / 2 * P

2. CLK[2]= FIN or FIN/2

Std: 10mA

(default)

High: 24mA

+/- 200ppm

tuning.

One output pin can be

configured as

1. CLK2 = FIN or FIN/2

2. FSEL - input

3. OE - input

2

4 levels of pump

current setting

PIN DESCRIPTION

Pin #

Name

(M)SOP-8

Type

Description

XIN/FIN

1

I

Crystal or Reference input pin

GND

2

P

GND connection

CLK[0:1]

3,4

O

Programmable Clock Output [note:CLK0=~CLK1]

VDD

5

P

VDD connection

DNC

6

-

Do No Connect

CLK2, OE, FSEL

7

B

This programmable I/O pin can be configured as CLK2

(

FIN or FIN/2) output, or OE input, or Frequency

Selection (FSEL) input pin. This pin has an internal 60K

pull up resistor.

State

OE

FSEL

0

Tristate

CLK[0:1]

Select Bank ’0’

ROM

1 (default)

Normal

mode

Select Bank ‘1’

ROM

XOUT

8

O

Crystal output pin