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PL611-20XXXMC-R 数据表(PDF) 3 Page - PhaseLink Corporation |
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PL611-20XXXMC-R 数据表(HTML) 3 Page - PhaseLink Corporation |
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3 / 7 page ![]() PL611-20 Programmable Quick Turn ClockTM 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 Rev 07/06/05 Page 3 DIE SPECIFICATION PAD LAYOUT AND DIE ID Name Value Size 31.5x55.1 mil Reverse side GND Pad Opening 80 micron x 80 micron Die Thickness 10 mil Note: CLK0=CLK1 PAD ASSIGNMENT and DESCRIPTION Die Pads Name Pad # X (µm) Y(µm) Type Description XIN 1 101.5 1274.0 I Crystal input. 2 101.5 1075.0 GND 3 101.5 878.4 P GND connection. CLK0 4 101.5 671.8 O Optional same frequency clock output (CLK0=CLK1). If the clock output is not used, the pad should remain as ‘Do Not Connect (DNC). CLK1 5 101.5 425.0 O Programmable Clock Output. VDD 6 697 483.0 VDD 7 697 790.0 P VDD connection. CLK2, OE, FSEL 8 697 1024.0 O This programmable I/O pin can be configured as CLK2 (FIN or FIN/2) output, or OE input, or Frequency Selection (FSEL) input pin. This pin has an internal 60KΩ pull up resistor. State OE FSEL 0 Tristate CLK[0:1] Select Freq. ‘1’ 1 (default) Normal mode Select Freq. ‘2’ XOUT 9 697 1274.0 O Crystal output. XIN GND GND CLK0 1 2 3 4 5 9 6 7 8 XOUT CLK2, OE, FSEL VDD VDD 1 2 3 4 5 9 6 7 8 CLK1 |
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