PLL102-10

Low Skew Output Buffer

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3. Switching Characteristics

PARAMETERS

SYMBOL

DESCRIPTION

MIN.

TYP.

MAX.

UNITS

Output Frequency

t1

50

120

MHz

Duty Cycle

DC

Measured at VDD/2,

45

50

55

%

Rise Time

Measured between 10%

1.2

1.5

ns

Fall Time

Measured between 90%

1.2

1.5

ns

Output to Output Skew

All outputs equally loaded,

250

ps

Delay, REF Rising Edge to

CLKOUT Rising Edge

Measured at VDD/2

0

±350

ps

Device to Device Skew

CLKOUT pins of devices

0

700

ps

Cycle to Cycle Jitter

Measured at 100MHz

60

ps peak

PLL Lock Time

Stable power supply, valid

clock presented on REF pin

1.0

ms

Jitter; Absolute Jitter

At 10,000 cycles, low jitter

input signal

20

50

ps

Jitter; 1-sigma

At 10,000 cycles, low jitter

input signal

9

15

ps

SWITCHING WAVEFORMS

Duty Cycle Timing

t1

t2

VDD/2

VDD/2

VDD/2

Output - Output Skew

VDD/2

VDD/2

T

SKEW

Output

Output