PL680-37OCL-R datasheet(7/10 Pages) PLL

部件名	PL680-37OCL-R

功能描述	38-640MHz Low Phase Noise XO

PDF	10 Pages

Scroll/Zoom	100%

制造商	PLL [PhaseLink Corporation]

网页	http://www.phaselink.com

标志

7 / 10 page

(Preliminary)

PL680-37/38/39

38-640MHz Low Phase Noise XO

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 7

10. PECL Electrical Characteristics

PARAMETERS

SYMBOL

CONDITIONS

MIN.

MAX.

UNITS

Output High Voltage

VOH

VDD – 1.025

Output Low Voltage

VOL

RL = 50

Ω to (VDD – 2V)

(see figure)

VDD – 1.620

11. PECL Switching Characteristics

PARAMETERS

SYMBOL

FREQ.

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Clock Rise & Fall Times

<150MHz

0.2

0.5

0.7

Clock Rise & Fall Times

>150MHz

<320MHz

0.2

0.4

0.55

Clock Rise & Fall Times

tr &tf

0.2

0.3

0.45

OUT

Ω

PECL Levels Test Circuit

PECL Transistion Time Waveform

OUT

50%

20%

80%

VDD

DUTY CYCLE

45 - 55%

55 - 45%

50%

OUT

SKEW

PECL Output Skew

2.0V

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