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PLL602-14OC-R 数据表(PDF) 3 Page - PhaseLink Corporation |
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PLL602-14OC-R 数据表(HTML) 3 Page - PhaseLink Corporation |
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3 / 5 page ![]() PLL602-14 192MHz – 400MHz Low Phase Noise LVDS XO (12 – 25MHz Crystal) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 3 3. General Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Supply Current, Dynamic (with Loaded Outputs) IDD LVDS 60 mA Operating Voltage VDD 2.97 3.63 V Output Clock Duty Cycle @ 1.25V (LVDS) 45 50 55 % Short Circuit Current ±50 mA 4. Jitter and Phase Noise Specification PARAMETERS CONDITIONS MIN. TYP. MAX. UNITS Period jitter RMS With capacitive decoupling between VDD and GND. 5 ps Accumulated jitter RMS With capacitive decoupling between VDD and GND. Over 10,000 cycles. 11 ps Phase Noise relative to carrier 311MHz @100Hz offset -90 dBc/Hz Phase Noise relative to carrier 311MHz @1kHz offset -114 dBc/Hz Phase Noise relative to carrier 311MHz @10kHz offset -134 dBc/Hz Phase Noise relative to carrier 311MHz @100kHz offset -134 dBc/Hz |
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