19

AT25DF512C

DS-25DF512C–030E–2/2017

11.1.3 WPP Bit

The WPP bit can be read to determine if the WP pin has been asserted or not.

11.1.4 BP0 Bit

modified to change the state of the software protection to allow the entire memory array to be protected or unprotected.

When the BP0 bit is in the logical “0” state, then the entire memory array is unprotected. When the BP0 bit is in the logical

“1” state, then the entire memory array is protected against program and erase operations.

11.1.5 WEL Bit

The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is in the logical “0” state,

the device will not accept any Byte/Page Program, erase, Program OTP Security Register, or Write Status Register

commands. The WEL bit defaults to the logical “0” state after a device power-up or reset operation. In addition, the WEL

bit will be reset to the logical “0” state automatically under the following conditions:



Write Disable operation completes successfully



Write Status Register operation completes successfully or aborts



Program OTP Security Register operation completes successfully or aborts



Byte/Page Program operation completes successfully or aborts



Block Erase operation completes successfully or aborts



Chip Erase operation completes successfully or aborts



Hold condition aborts

If the WEL bit is in the logical “1” state, it will not be reset to a logical “0” if an operation aborts due to an incomplete or

unrecognized opcode being clocked into the device before the CS pin is deasserted. In order for the WEL bit to be reset

when an operation aborts prematurely, the entire opcode for a Byte/Page Program, erase, Program OTP Security

Register, or Write Status Register command must have been clocked into the device.

11.1.6 RDY/BSY Bit

The RDY/BSY bit is used to determine whether or not an internal operation, such as a program or erase, is in progress.

To poll the RDY/BSY bit to detect the completion of a program or erase cycle, new Status Register data must be

continually clocked out of the device until the state of the RDY/BSY bit changes from a logical “1” to a logical “0”.Note that

the RDY/BSY bit can be read either from Status Register Byte 1 or from Status Register Byte 2.

11.1.7 RSTE Bit

The RSTE bit is used to enable or disable the Reset command. When the RSTE bit is in the Logical 0 state (the default

state after power-up), the Reset command is disabled and any attempts to reset the device using the Reset command

will be ignored. When the RSTE bit is in the Logical 1 state, the Reset command is enabled.

The RSTE bit will retain its state as long as power is applied to the device. Once set to the Logical 1 state, the RSTE bit

will remain in that state until it is modified using the Write Status Register Byte 2 command or until the device has been

power cycled. The Reset command itself will not change the state of the RSTE bit.

Table 11-2. Status Register Format – Byte 2

Name

Description

7

RES

Reserved for future use

R

0

Reserved for future use

6

RES

Reserved for future use

R

0

Reserved for future use

5

RES

Reserved for future use

R

0

Reserved for future use