PLL602-04

Low Phase Noise CMOS XO (96MHz to 200MHz)

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1

FEATURES

• Low phase noise XO for the 96MHz to 200MHz

range (-125 dBc at 10kHz offset).

• 12 to 25MHz crystal input.

• Integrated crystal load capacitor: no external

load capacitor required.

• Low jitter (RMS): 4ps period jitter (1 sigma).

• Selectable High Drive (30mA) or Standard Drive

(10mA) output.

• 3.3V operation.

• Available in 8-Pin TSSOP or SOIC.

DESCRIPTION

The PLL602-04 is a low cost, high performance and

low phase noise XO, providing less than -125 dBc at

10kHz offset in the 96MHz to 200MHz operating

range. The very low jitter (4ps RMS period jitter)

makes this chip ideal for 155.52MHz SONET and

SDH applications, and for 125MHz and 106.25MHz

applications. Input crystal can range from 12 to

25MHz (fundamental resonant mode).

PIN CONFIGURATION

OUTPUT RANGE

MULTIPLIER

FREQUENCY

RANGE

OUTPUT

BUFFER

x8

96 - 200MHz

CMOS

BLOCK DIAGRAM

Reference

Divider

Phase

Comparator

Charge

Pump

Loop

Filter

VCO

VCO

Divider

XTAL

OSC

OE

XIN

XOUT

CLK

1

2

3

45

6

7

8

CLK

VDD

OE^

XIN

GND

N/C

XOUT

GND

Note: ^ denotes internal pull up