(Preliminary)

PL680-37/38/39

38-640MHz Low Phase Noise XO

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 5

4. Jitter Specifications

PARAMETERS

CONDITIONS

FREQUENCY

MIN.

TYP.

MAX.

UNITS

106.25MHz

0.4

0.5

156.25MHz

0.4

0.5

212.5MHz

0.4

0.5

312.5MHz

0.4

0.5

Integrated jitter RMS

Integrated 12 kHz to 20 MHz

622.08MHz

0.4

0.5

ps

106.25MHz

3

5

156.25MHz

3

5

212.5MHz

3

5

312.5MHz

3

5

Period jitter RMS

With capacitive decoupling

between VDD and GND.

Over 10,000 cycles.

622.08MHz

6

8

ps

106.25MHz

20

30

156.25MHz

20

30

212.5MHz

20

30

312.5MHz

20

30

Period jitter Peak-to-

Peak

With capacitive decoupling

between VDD and GND.

Over 10,000 cycles.

622.08MHz

40

50

ps

5. Phase Noise Specifications

PARAMETERS

FREQ.

@10Hz

@100Hz

@1kHz

@10kHz

@100kHz

@1M

@10M

UNITS

106.25MHz

-66

-96

-122

-132

-126

-144

-150

156.25MHz

-62

-92

-120

-132

-128

-140

-150

212.5MHz

-62

-92

-118

-126

-120

-140

-150

312.5MHz

-59

-85

-117

-128

-125

-139

-148

Phase Noise

relative to carrier

(typical)

622.08MHz

-49

-84

-111

-120

-118

-128

-138

dBc/Hz

6. CMOS Electrical Characteristics

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

30

mA

Output drive current

30

mA

Output Clock Rise/Fall Time

0.3V ~ 3.0V with 15 pF load

0.7

ns

Output Clock Rise/Fall Time

20%-80% with 50Ω Load

0.3

ns