PLL650-03

Low EMI Network LAN Clock

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 2

PIN DESCRIPTIONS

Name

Number

Type

Description

XIN

1

I

XOUT/50MHz_OE

2

B

Crystal connection pin. At power-up, this pin latches 50MHz_OE (output

enable selector for all 50MHz outputs. Disabled when 50MHz_OE is logical

zero. Has 120k

Ω internal pull up resistor.

50MHz/FS(0:2)

5,7,8

B

50MHz outputs. These pins latch FS(0:2) value at power-up. Pins 5 and 7

have 60k

Ω internal pull up resistors.

50MHz/SS0

9

B

50MHz output. This pin latches SS0 value at power-up (tri-level pin). SS0

value is used to control the spread spectrum function.

SDRAMx2

11

O

SDRAM outputs with double drive strength determined by FS(0:1) value.

25MHz/100MHz

14

O

25MHz (reference) or 100MHz output. Can be disabled with FS2 = M.

VDD

4,10,15,16

P

3.3V power supply.

GND

3,6,12,13

P

Ground.

SPREAD SPECTRUM SELECTION TABLE

SS0

SST

0

±0.75% Center

M

OFF

1

±0.5% Center

FUNCTIONAL DESCRIPTION

Selectable spread spectrum and output frequencies

The PLL650-03 provides selectable spread spectrum modulation and selectable output frequencies. Selection is made by

connecting specific pins to a logical “zero” or “one”, or by leaving them not connected (tri-level inputs or internal pull-up)

according to the frequency and spread spectrum selection tables shown on pages 1 and 2 respectively.

In order to reduce pin usage, the PLL650-03 uses tri-level input pins. These pins allow 3 levels for input selection: namely, 0

(Connect to GND), 1 (Connect to VDD), M (Do not connect). Thus, unlike the two-level selection pins, the tri-level input pins are

in the “M” (mid) state when not connected. In order to connect a tri-level pin to a logical “zero”, the pin must be connected to

GND. Likewise, in order to connect to a logical “one” the pin must be connected to VDD.

Pin 2 (XOUT/50MHz_OE) is a bi-directional pin used to disable the 50MHz outputs. Pin 5 (FS0) and pin 7 (FS1) are bi-

directional pins used to select the SDRAM output frequency upon power-up. Pin 8 (FS2) and pin 9 (SS0) are bi-directional pins

used to select the output frequency of pin 14, as shown in the frequency table on page 1, and to control the Spread Spectrum

modulation for EMI reduction. After the input signals have been latched, pins 5, 7, 8, 9, and 11 serve as 50 MHz frequency

outputs.