PLL601-02

Low Phase Noise PLL Clock Multiplier

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 3

3. DC Specifications

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Operating Voltage

2.97

3.63

V

Input High Voltage

2

V

Input Low Voltage

0.8

V

Input High Voltage

For XIN pin

+ 1

V

Input Low Voltage

For XIN pin

− 1

V

Output High Voltage

2.4

V

Output Low Voltage

0.4

V

Output High Voltage At

CMOS Level

V

Operating Supply Current

No Load

35

mA

Short-circuit Current

±50

mA

Input Capacitance

OE, Select Pins

5

pF

4. Crystal Specifications

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Crystal Resonator Frequency

Parallel Fundamental Mode

10

27

MHz

Crystal Loading Capacitance

Rating

15

pF

5. Jitter Specifications

PARAMETERS

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Period jitter RMS

With capacitive decoupling

between VDD and GND

6.4

ps

Accumulated jitter RMS

With capacitive decoupling

between VDD and GND

9.4

ps

Phase Noise, relative to carrier, 155Mhz(x8)

100Hz offset, 3.3V

-103

dBc/Hz

Phase Noise, relative to carrier, 155Mhz(x8)

1kHz offset, 3.3V

-126

dBc/Hz

Phase Noise, relative to carrier, 155Mhz(x8)

10kHz offset, 3.3V

-133

dBc/Hz

Phase Noise, relative to carrier, 155Mhz(x8)

100kHz offset, 3.3V

-128

dBc/Hz