PLL650-07

LOW COST Network LAN Clock SOURCE

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1

FEATURES

• Full CMOS output swing with 40-mA output drive

capability. 25-mA output drive at TTL level.

• Advanced, low power, sub-micron CMOS processes.

• 25MHz fundamental crystal or clock input.

• 2 outputs fixed at 50MHz, 2 outputs fixed at 25MHz .

• Zero PPM synthesis error in all clocks.

• Ideal for Network switches.

• 3.3V operation.

•

DESCRIPTION

The PLL650-07 is a low cost, low jitter, high

performance clock synthesizer. With PhaseLink’s

proprietary analog Phase Locked Loop techniques, this

device can produce multiple clock outputs from a 25.0MHz

crystal or reference clock. This makes the PLL650-07 an

excellent choice for systems requiring clocking for network

chips and ASICs.

PIN CONFIGURATION

BLOCK DIAGRAM

50MHz

Post

Divider

XTAL

OSC

XIN

XOUT

Phase

Detector

Charge

Pump

Loop

Filter

VCO

VCO

Divider

+

2

2

25MHz

1

2

3

4

5

6

7

8

9

10

11

12

13

14

XIN

VDDA

NC

GND

25MHz

GND25M

25MHz

XOUT

GNDA

VDD50M

50MHz

GND50M

50MHz

VDD25M